Abstract

In this paper, the structural and electronic properties of epitaxial graphene (EG) grown on 8°-off 4H–SiC (0001) by high temperature thermal processes have been extensively investigated by a combination of several high resolution characterization techniques. The increase in the number of graphene layers with the growth temperature (from 1600 to 1700°C) was studied by microRaman spectroscopy and high resolution transmission electron microscopy (HRTEM) on cross-sectioned samples. The few layers of graphene reside on a stepped SiC surface with alternating (0001) terraces and (11−2n) facets. Peculiar corrugations (wrinkles) in the graphene membrane preferentially oriented perpendicularly to the substrate steps were also observed. Motivated by recent atomic resolution studies of the EG/SiC interface revealing a local delamination of the interfacial C buffer from the (11−2n) facets, we searched for a correlation of these interfacial structural properties with the macroscopic electronic transport in EG field effect transistors (FETs). In particular, electrical characterization of EG top gated FETs fabricated with the channel length parallel or perpendicular to the substrate steps revealed a peculiar anisotropy of the channel conductance with respect to the steps' orientation. This effect was explained in terms of a local enhancement of EG resistance on the (11−2n) facets with respect to the (0001) basal plane, which is consistent with a reduced doping due to the local buffer layer delamination from those facets. Furthermore, scanning probe microscopy-based local electron mean free path measurements on EG showed a ~3× enhancement of mean free path on the buffer-layer-free (11−2n) facets with respect to (0001) terraces, probably associated to a strong reduction of Coulomb scattering effects on graphene's electrons.

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