High rejection low-pass-filter design using integrated passive device technology for Chip-Scale Module Package

Abstract

Currently, there is widespread adoption of silicon-based technologies for the implementation of radio frequency (RF) integrated passive devices (IPDs) because of their low-cost, small footprint and high performance. These devices are receiving increased attention for developing front-end-module (FEM) applications in mobile communication systems. This paper discusses the design of low pass filters (LPF) for use in the GHz range with high harmonic rejection. In large modules, these filters make use of co-planar ground planes and lumped IPD technology on a silicon substrate CSMP (Chip Scale Module Package). The use of coplanar ground in such modules introduces unique performance constraints, especially in filters requiring high harmonic rejection. These problems are discussed, along with design approaches to help mitigate them.