A Miniaturized Bandpass Filter Design and Verification with De-embedding Technology in SiP Solutions

Abstract

In this paper, the design, trade-offs, chip-level simulation and verification of a miniaturized radio frequency (RF) filter with low insertion loss and high rejection have been demonstrated. The proposed architecture of the bandpass filter (BPF) consists of a multi-order cascaded LC network and ground coupled sections which introduce resonant zeros and poles in the passband. The BPFs with two topologies are presented in this work, followed by performance comparison and investigation. Implemented with a high resistivity silicon integrated passive device (IPD) process, the BPF features a compact die area of 0.75 mm2 and 0.6 mm2 respectively, including seal ring at each side of the chip. The IPD filter design is validated with a probing setup by locating the IPD chips on a test board with wire bonding package. In order to evaluate the package degradation on the overall performance, the bonding wires and test fixtures on the test board have been respectively modeled and de-embedded, together with an on-board calibration during the probe measurement.