Abstract
A design technique for an asynchronous Analog-to-Digital Converter (ADC) is presented. The proposed design retains a clockless level crossing sampling technique, and then applies a Wavelet Neural Network (WNN) technique. High-level simulation results are shown for various ADC resolutions. The Signal to Noise and Distortion Ratio (SNDR) achieved for 4-bit ADC systems are presented. It has been shown that a 4-bit system with the proposed asynchronous ADC architecture using a WNN technique achieves an Effective Number Of Bits (ENOB) of up to 38 bits depending on the input frequency and resolution.
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