A pipeline analogue to digital converter in 0.35 μm CMOS

Abstract

This paper describes an 8-bit, 130 MS/s pipelined analogue to digital converter (ADC) implemented in 0.35 μm CMOS technology from Austria Microsystems (AMS). The specifications for the design presented in this paper are in terms sampling frequency, power consumption, integral non-linearity (INL), differential non-linearity (DNL), signal to noise and distortion ratio (SNDR), and signal to quantization noise ratio (SQNR). The design achieved a SNDR of 47 dB corresponding to an effective number of bits (ENOB) of 7.5 bits. The system was designed to operate with a front-end working according to the Digital European Cordless Telecommunications (DECT) standard.