Abstract
Chip designers are putting more and more components on a single chip. The more complex the function of the chip, greater is the demand on signal and power lines leading to a high pin-count chip. On the other hand, system designers are preferring surface mount technology which leads to cost savings in the printed circuit board. Caught in this cleft is the semiconductor packaging engineer, who has to design new innovative packages which are not only of high pin-count but also amenable to new assembly technique of surface mounting. In this paper new packaging techniques such as PGAs, PLCCs, LCCs, LLCCs, PQFPs and TAB are surveyed.PLCC is the most cost effective high pin-count packaging technology. Details of PLCC packaging process along with relevant equipment issues are also presented in this paper.Finally, some guidelines for process optimization and good practices are enumerated.
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