High performance two-stage charge-pump for spur reduction in CMOS PLL

Abstract

This paper proposes a charge pump that minimizes the current mismatch and keeps the constant current across a wide range of output voltage. The charge pump is a two-stage circuit which is composed of the conventional push-pull charge pump and the compensation circuit. The compensation circuit has a feedback biasing circuit and an op-amp to act as a voltage follower. The features of feedback circuit and voltage follower are the important elements to reduce the current mismatch. The proposed charge pump is applied in 2 GHz PLL to check out the noise spectrum of the spur and phase offset which are occurred from the current mismatch. The proposed charge pump indicates that the current mismatch is less than 5 % over the voltage range of 0.30 ~ 1.45 V which covers almost 63 % of the 1.8 V supply voltage. The spur in PLL is obtained to be -63.7 dBc, while the conventional charge pump provides the spur of -36.2 dBc in the same PLL.