Abstract
This paper describes a fully programmable 6 processor die that was implemented in IBM's 130 nanometer 8SF process. It is capable of operating as two triple voted processors each with 6 Mbytes of Embedded Dynamic Random Access Memory (EDRAM) or 6 independent processors each with 2 Mbytes of EDRAM. In triple vote mode the processor counts and recovers from single event upsets. It supports external Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), and has two Spacewire ports, a 4 GBit input port, and a 4 Gbit output port. The processor core with memory performs approximately 2.5 Giga Floating Point Operations Per Second (GFLOPS) per Watt, with worst case input/output power its performance is approximately 1 GFLOPS per Watt. The processor's efficient messaging allows hundreds of processors to be applied to applications such as radar.
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