High performance robust audio event recognition system based on FPGA platform

Abstract

Audio event recognition is applied in many novel application areas. Opposing the deep CNN, 1-max pooling CNN is a simple, but efficient CNN architecture for robust audio event recognition. This study proposes a parallel architecture to accelerate robust audio event recognition. To implement this in hardware, we evaluate the precision of 1-max pooling CNN model and propose an approximate algorithm to replace the complex calculation in spectral image feature (SIF) extraction. We then propose a scalable parallel structure of SIF extraction and 1-max pooling CNN. The SIF extraction unit has eight parallelisms and the 1-Max Pooling CNN accelerator has 40 processor elements (PEs) in our implementation. The entire system is implemented on the Xilinx VC709 board. The average performance of our FPGA accelerator is 675.7 fps under 100 MHz working frequency, which is about 31.9× speed-up compare with CPU. We further implement a small-scale FPGA array with four Xilinx FPGA for robust audio event recognition. To communicate between the four FPGA and the host, we design a route protocol based on source route algorithm.