High-Performance Reconfigurable Computing

Khaled Benkrid,Kentaro Sano,Esam El-Araby,Thomas Steinke,Miaoqing Huang

doi:10.1155/2012/104963

Abstract

1 School of Engineering, The University of Edinburgh, Edinburgh EH9 3JL, UK 2Electrical Engineering and Computer Science, The Catholic University of America, Washington, DC 20064, USA 3Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR 72701, USA 4Graduate School of Information Sciences, Tohoku University, 6-6-01 Aramaki Aza Aoba, Sendai 980-8579, Japan 5Zuse-Institut Berlin (ZIB), Takustrase 7, 14195 Berlin-Dahlem, Germany

Highlights

The issue presents a number of architectural concerns in the design of high-performance reconfigurable computing (HPRC) systems, namely: reconfigurable hardware architecture, communication network design, and arithmetic design
Received 28 February 2012; Accepted 28 February 2012. This special issue presents some of the latest developments in the burgeoning area of high-performance reconfigurable computing (HPRC) which aims to harness the high-performance and low power of reconfigurable hardware in the forms of field programmable gate arrays (FPGAs) in highperformance computing (HPC) applications
The issue presents a number of architectural concerns in the design of HPRC systems, namely: reconfigurable hardware architecture, communication network design, and arithmetic design

Summary

Introduction

The issue presents a number of architectural concerns in the design of HPRC systems, namely: reconfigurable hardware architecture, communication network design, and arithmetic design. This special issue presents some of the latest developments in the burgeoning area of high-performance reconfigurable computing (HPRC) which aims to harness the high-performance and low power of reconfigurable hardware in the forms of field programmable gate arrays (FPGAs) in highperformance computing (HPC) applications. Starke et al from the University of Kiel in Germany present the use of a massively parallel FPGA platform, called RIVYERA, in the high-performance and low-power optimization of investment strategies.

Results

Conclusion