Abstract

Power consumption is the most crucial challenge for advanced IC with billions of transistors. High mobility Ge CMOS is one of the promising candidates to further lower the power consumption. Unfortunately, the ohmic contact in Ge nMOSFET suffers from Fermi-level pinning to valance band (Ev). It is also hard to form n + /p Ge junction by standard ion implantation due to the poor dopant activation by rapid thermal annealing (RTA) and fast impurity diffusion. Here high performance metal-gate/high-k/(111)-Ge nMOSFET was achieved with good 1.05 junction ideality factor (n), large ~5 orders on/off junction current, and higher mobility than SiO 2 /Si data at wide range carrier density (N s ) at small 0.85 nm equivalent-oxide thickness (EOT). The excellent n + /p Ge junction is attributed to the fast 30-ns laser annealing (LA) and YbGe 2-x /n-Ge contact with less Fermi-level pinning.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.