Ge technology beyond Si CMOS

Abstract

To save energy, low voltage operation is the most important criterion for CMOS ICs. To reach this goal, high mobility new channel materials are required for CMOS ICs at ≤ 14 nm technology nodes. The high electron mobility InGaAs nMOSFET and high hole mobility Ge pMOSFET were proposed for CMOS at 0.5 V operation, since the poor hole mobility of InGaAs makes it unsuitable for all InGaAs CMOS. However, the epitaxial InGaAs nMOSFET on Si faces fundamental material challenges with large defects and high leakage current. Although dislocation-defects-free Ge-on-Insulator (GeOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI), and selective GeOI on Si were pioneered by us, it is still difficult to reach InGaAs-nMOS/Ge-pMOS CMOS targeting to ≤ 14 nm CMOS. In contrast, Ge is the ideal candidate for all Ge CMOS logic due to both higher electron and hole mobility than Si. Significantly higher (2.6X) hole mobility of GeOI pMOSFET than universal SiO2/Si value was reached at a medium 0.5 MV/cm effective electric field (Eejf) and 1.4 nm equivalent-oxide-thickness (EOT). Nevertheless, the Ge nMOSFET suffers from large EOT and fast mobility degradation with increasing Eeff, due to the surface Fermi-level pinning to valance band, poor high-κ/Ge interface and low dopant activation. Using novel laser annealing and proper gate stack, small EOT of 0.95 nm, small sub-threshold swing of 106 mV/dec, and 40% better high-field mobility than universal SiO2/Si data were achieved in Ge nMOSFET. Such all-Ge CMOS has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS CMOS platform.