High Performance Multistage CMOS Charge Pump Circuit

Abstract

CMOS charge pump circuits are used to provide different voltage level on single chip to operate different circuits on the chip itself. Four stage charge pump circuit is presented in this paper. Also output of all the stages can be taken simultaneously to drive any other circuit on same chip. In our research by optimizing W/L ratio of all the transistors, silicon area utilized by the circuit is reduced to a great extent while maintaining satisfactory speed of operation of the circuit as well as comparatively low ripples at output. Transistors used in our design are having area of one fifteenth as compared to previous design. Thus area efficiency is one of the achievements of our design. Output voltage of four stage charge pump at no load is 16.41 volt and rise time is 19.71 µ s which is 80.29% less than that of previous design and ripples is 20 mV peak to peak. Output voltage with load condition C L = 100pF, R L = 500KΩ is 9.13 volt and rise time is 57.39 µs which is 14.34% less than that of previous design. In our design power consumption at no load is 8.5 µW which is 15% less than that of previous design. Thus area and power consumption are decreased and speed of operation is also increased in our present work.