A CMOS Charge Pump Circuit with Short Turn-on Time for Low-spur PLL Synthesizers

Abstract

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 μA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.