High Performance Isolated LDMOS with Source Spacer and Asymmetric Hetero-doped Architectures

Abstract

A novel isolated LDMOS structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain, is proposed. The asymmetric hetero-doped source/drain reduces the on-state resistance of the transistor due to the high n-type doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n+ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped source/drain structure allows the isolated LDMOS to have a high current handling capability with a small device size. Measured results show that a 24 V breakdown voltage new device with a low cost two-layer metal (Al) back-end achieves very low R (sp, on) of 16.6 mOmega.mm2. Furthermore, the new device with 65 V high-side capability achieves good isolation performance even when switching source/drain to -20 V and also gets a cut-off frequency of 13 GHz at a gate voltage of 5.5 V