Abstract

Coherent Signal-Subspace (CSS) is a technique to separate the wide frequency band into narrowband components which can be applied in many applications such as smart antennas for wireless communications and radar. However, CSS is computationally intensive and may not achieve the real-time requirement. Therefore, this work aims to propose an efficient implementation of the CSS method on Field-Programmable Gate Array (FPGA) to achieve the desired performance. Different parallelization and optimization techniques such as loop unrolling, loop pipelining, dataflow, and loop flattening are adopted and applied to explore the opportunities of any computation and storage that could be eliminated in order to achieve high efficiency. The results of the proposed optimized implementation achieve the highest performance compared with other related implementations.

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