Loop parallelization and pipelining implementation of AES algorithm using OpenMP and FPGA

Abstract

AES (Advanced Encryption Standard) is an effective encryption algorithm in applications like Internet to provide cyber security and also in smart cards. Multi-core and Field-Programmable Gate Arrays (FPGAs) are the promising solution for the performance up gradation. The main focus of this paper is to increase the throughput of the AES algorithm through hardware and software techniques. Various approaches for efficient hardware implementation of the AES algorithm is based on architectural optimization techniques like pipelining, loop unrolling and iterative design. Here we have adopted pipelining technique to increase the speed of the algorithm by processing multiple rounds simultaneously. Software parallelization techniques with OpenMP standard is used to increase the speedup of the algorithm compared to its sequential version. A pipelined architecture AES-128 core is implemented using Xilinx xc5vlx110t-1 device can achieve a throughput of 31.25Gbps which is more effective than previous ASIC implementations. By implementing the AES algorithm using OpenMP we achieve speed up of 1.08 in the dual core processor.