Abstract
In this paper, we present a gate-all-around silicon nanowire transistor (GAA SNWT) with a triangular cross section by simulation and experiments. Through the TCAD simulation, it was found that with the same nanowire width, the triangular cross-sectional SNWT was superior to the circular or quadrate one in terms of the subthreshold swing, on/off ratio, and SCE immunity, which resulted from the smallest equivalent distance from the nanowire center to the surface in triangular SNWTs. Following this, we fabricated triangular cross-sectional GAA SNWTs with a nanowire width down to 20 nm by TMAH wet etching. This process featured its self-stopped etching behavior on a silicon (1 1 1) crystal plane, which made the triangular cross section smooth and controllable. The fabricated triangular SNWT showed an excellent performance with a large Ion/Ioff ratio (~107), low SS (85 mV/dec), and preferable DIBL (63 mV/V). Finally, the surface roughness mobility of the fabricated device at a low temperature was also extracted to confirm the benefit of a stable cross section.
Highlights
The semiconductor industry is driven by the continuous device scaling of the metal-oxidesemiconductor field-effect transistor (MOSFET) according to Moore’s Law
Enormous attention has been paid to gate-all-around silicon nanowire transistors (GAA SNWT) due to their extraordinary electrostatic controllability, and they are considered as one of the most promising candidates in the sub-10nm technology node
GAA SNWT still has some issues relating to its performance and process which need to be addressed before it is used in commercial applications
Summary
The semiconductor industry is driven by the continuous device scaling of the metal-oxidesemiconductor field-effect transistor (MOSFET) according to Moore’s Law. The second challenge comes from the lack of a feasible method for fabricating three-dimension suspended silicon nanowire with an accurately controlled size and cross-sectional shape [7], which is beneficial to the device variability suppression and mobility enhancement. We proposed a triangular shape to be the optimized cross section for the nanowire process flow should be highly compatible with the traditional CMOS technology nanowire and toitsconfirm its advantages in scalability and performance by TCAD simulation. The second low-temperature mobilitythe characterization waswet thenetching carried out totoevaluate benefit to the nanowire channel with a stable, smooth, and precisely-size-controlled inverted triangular cross suppression of surface roughness scattering by the self-limited structure. The low-temperature mobility characterization was carried out to evaluate the benefit to the suppression of surface roughness scattering by the self-limited structure
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
