High Performance Four Segment Error Tolerant Adder for 8-bit Pixel Depth Image Processing Applications

Abstract

This research proposes a high-performance Carry Select Approximate Full Adder (CSAFA) with one error out of the eight possible output cases for high accuracy 8-bit pixel depth image processing applications. The logic optimization of the proposed CSAFA module is based on a structural hierarchy of AND-OR logic and multiplexer based pre-computation selection logic which reduces the critical path switching activity. The proposed method has the advantage of higher speed, lower power consumption and improved area efficiency. Simulation results show that the proposed CSAFA reduces the critical path delay, power consumption, area, Power-Delay Product (PDP) and Area-Delay Product (ADP) by 26.81%, 44.99%, 23.53%, 59.74%, 44.03% respectively, compared to the existing Conventional Full Adder (CFA). Further, the proposed structure incorporates the 8-bit Error Tolerant Adder (ETA-CSAFA and ETA-CSAFA1) designs. When comparing with 99.5992% Computational Accuracy (CA), the proposed ETA-CSAFA1 design exhibits 0.26% less CA and it offers a savings of 27.82% PDP and 34.39% ADP with respect to the existing ETA-2LOA architecture. The results can be substantiated with an example, a 4-bit accurate part based ETA-CSAFA1 implemented with the proposed approach almost achieves the same CA, while simultaneously reducing the power consumption by 18.14% with respect to the existing best 6-bit accurate part based ETA-2LOA architecture for 8-bit image processing applications.