High Performance Computing Package With Chip Module on Substrate Solutions

Abstract

Abstract With die size increasing and bump pitch decreasing on FCBGA (flip chip ball grid array), warpage is the first challenge that processes of package assembly and SMT (surface mount technology) will have. The main factor is CTE (coefficient of thermal expansion) mismatch between chip and substrate. The larger die size, the more significant elongation difference which could cause warpage. Furthermore, serious warpage can cause manufacture difficulties, such as bump bridge, bump non-wet and underfill (UF) void. As the result, in order to control package warpage, additional force, such as high modulus UF or metal heat sink are usually applied to restrict package deformation. However, the more additional force is applied, the more stress may be transferred to chip and causes chip corner or UF crack where easily cause stress concentration. In this paper, large package > 70 * 70 mm is studied for the challenges of on substrate process and reliability, meanwhile simulation is performed for stress prediction. In addition, possible solutions from material and process are discussed and studied.