High performance Bulk FinFET with bottom spacer

Abstract

In this paper we propose a novel bottom spacer Bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. It solves the problem associated with the width quantization effect with optimized spacer height. Using well-calibrated device models and simulations, we have shown that Bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs using 3-D device simulation and design methodology.