High performance area efficient DA based FIR filter for concurrent decision feedback equalizer

Abstract

In this paper we proposed a novel Distributed Arithmetic (DA) based block FIR filters for design of decision feed back equalizers. Here a block FIR filter is designed using DA architecture and is implement for DFE architecture. By introducing block FIR filter architecture the throughput rate for the design is increased. The proposed distributed arithmetic architecture is implemented in application specific integrated circuit (ASIC) Synopsis design compiler tool using SAED 90 nm technology. The application of decision feed back equalizer is implemented in Matlab Simulink and Xilinx system generator tool. The obtained results shows 71% less area delay product (ADP) and 65% less energy delay product (EDP) when compared with the existing architecture and the performance of the design is very high. By using proposed DA based DFE architecture the ISI noises can be removed and is well suited for digital communication systems.