High performance analog operation of double gate transistors with the graded-channel architecture at low temperatures

Abstract

This work studies the use of channel engineering by means of graded-channel profile on double gate SOI MOSFETs for improving the analog performance and comparing their output characteristics with conventional double gate SOI transistors at low temperatures from room temperature down to 95 K. Two-dimensional simulations performed here provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs, showing significantly reduced electric field and hence impact ionization rate, which is well known to plague the output characteristics of SOI MOSFETs in the low temperature range. The Early voltage degrades as the temperature decreases but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150–300 K due to compensation provided by the transconductance over drain current ratio. The graded-channel structure can finally improve the intrinsic gain of conventional double gate transistor from 67 dB to 90 dB at 300 K. In the range of L LD/ L between 0.20 and 0.35, the gain reaches 90 dB and is weakly temperature-dependent with less than 10% reduction in the range of 300 K down to 95 K.