High Performance Advanced Encryption Standard system using Secure Double Rate Registers

Abstract

Power Analysis Attack (PAA) are a class of Side Channel Attacks (SCA) which is based on power consumption measurements whose major concern is the protection of secret data stored in cryptographic devices. This paper reports the advantages of Secure Double Rate Registers (SDRR) as a Register Transfer Level (RTL) countermeasure in order to increase the security of cryptographic devices against PAA. SDRR is exploited in AES 128 bit architecture, the random data in the entire clock cycle is evaluated by the combinational path. One of the main advantage is that our technique does not require duplication of combinational path to process the random data thereby limiting area overhead unlike previous RTL countermeasures. This work reported in this paper gives the comparative study between conventional advanced encryption standard (AES) algorithm with normal registers and AES algorithm with secure double rate registers (SDRR). This proposed system is implemented, simulated using Verilog HDL and synthesized by Xilinx tool.