High performance 2D transform hardware for future video coding

Abstract

Future Video Coding (FVC) is a new international video compression standard offering much better compression efficiency than previous video compression standards at the expense of much higher computational complexity. In this paper, two different high performance FVC 2D transform hardware are designed and implemented using Verilog HDL. They are the first FVC 2D transform hardware in the literature. They perform 2D DCT-II, DCT-V, DCT-VIII, DST-I, and DST-VII operations for 4x4 and 8x8 transform units. The first (baseline) hardware uses separate datapaths for each 1D transform. Since the second (reconfigurable) hardware uses two reconfigurable datapaths for all 1D transforms, it has smaller area than the baseline hardware. Since the baseline hardware uses data gating technique, it has lower energy consumption than the reconfigurable hardware. Therefore, the proposed FVC baseline 2D transform hardware can be used in high performance and low energy FVC encoders. The proposed FVC reconfigurable 2D transform hardware can be used in high performance and low cost FVC encoders.