Abstract
This paper describes the system and architecture design of a transceiver for transmission of data rates up to 1 Gb/s over the microwave radio channel. The transceiver implements adaptive modulation using high-order QAM constellations, includes a powerful LDPC error correction code which offers high coding gain and low error floor in addition to a more traditional Reed-Solomon based solution. To minimize the impact of the phase noise due to low cost oscillators an advanced carrier recovery scheme is used. The design choices and trade-offs involved in implementing the transceiver in different technologies, an FPGA based test chipset and two different structured ASIC technologies, are described in details. Implementation of the transceiver in a standard cell ASIC is ongoing.
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