High on-currents with highly strained Si nanowire MOSFETs

Abstract

In this work we demonstrate the benefit of high uniaxial tensile strain on the performances of Si nanowire (NW) MOSFETs. High uniaxial tensile strained Si NWs were realized by exploiting a “bridge technology” via patterning of an initial tensely strained Si on insulator (sSOI) into thin NWs with large relaxed pads, functionalized as stressors. Strained Si NW-arrays along <;110>/(100) direction with tensile strain values up to 2.2% were achieved. We have fabricated n-type Si NW-array MOSFETs with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN gate stack and NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> source/drain contacts. An I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> current increase was observed by a factor of 2 from 1.3% to 1.8% uniaxial tensely strained NW MOSFETs. The enhanced device performance is primarily attributed to a higher electron mobility in the highly strained Si NWs.