Abstract
We developed a 65-nm CMOS technology that could successfully integrate a novel porous low- k material, NCS. Using our nano-clustering technique, we obtained that NCS had a high compatibility between a very low dielectric constant and high framework strength. We successfully fabricated 11-levels Cu interconnects using hybrid-NCS structure. These interconnects had a high tolerance to the etching process and produced a smooth surface on the bottom of the trenches, with no via-fences, and no low- k voiding. They did not require a pore-sealing process. These high-performance hybrid-NCS/Cu multilevel interconnects met the 65-nm node requirements for Back-End of the Line, while maintaining sufficient robustness to support CMP, wire-bonding, and packaging processes. Hybrid-NCS/Cu multilevel interconnects are suitable for mass production and show excellent reliability for 65-nm node device requirements.
Published Version
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