Abstract
High-level synthesis (HLS) and OpenCL are the two leading high-level design platforms that are becoming widely used for programming FPGAs. Their proponents claim that these tools require little to no knowledge of the hardware design principles and can significantly improve developer's productivity. In this article, the author explore these two high-level design approaches from the point of view of a software developer. The author use Xilinx Vivado HLS C/C++ ver. 2019.1 and Xilinx SDAccel OpenCL ver. 2019.1 to implement a cross -correlation operation from scratch and synthesize it for a Xilinx u250 Alveo FPGA board.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
