High-Level Synthesis-Based Approach for Accelerating Scientific Codes on FPGAs

Abstract

High-level synthesis (HLS) and OpenCL are the two leading high-level design platforms that are becoming widely used for programming FPGAs. Their proponents claim that these tools require little to no knowledge of the hardware design principles and can significantly improve developer's productivity. In this article, the author explore these two high-level design approaches from the point of view of a software developer. The author use Xilinx Vivado HLS C/C++ ver. 2019.1 and Xilinx SDAccel OpenCL ver. 2019.1 to implement a cross -correlation operation from scratch and synthesize it for a Xilinx u250 Alveo FPGA board.