High-level model based calibration technique design for SAR ADC

Abstract

This article presents a method of developing and debugging algorithms for mixed-signal schemes using mathematical model. SAR ADC is used as an example to present the method. A divided capacitor array with is used in the mathematical model. The Laplase transform is used to replace differential integral equations with algebraic ones. The input dependence of the comparator on the switches in the capacitor array is the basis of the mathematical model. There are two additional models – capacitance mismatch model, which was performed by randomly adding the value of the uniform distribution from -0.01 to 0.01 unit of the smallest capacitance, and noise model, which was performed as randomly changing comparator offset. As a result, there is a mathematical model of SAR ADC with event-driven architecture. Switching of K0 sample switch and bit switches leads to changing of circuit state. Mismatch in the capacitor array during chip manufacturing leads to deterioration of key characteristics of ADC – signal-to-noise ratio and spurious-free dynamic range. There is an algorithm, that can calculate the capacitors mismatch and correct the output code. Such an algorithm shows the efficiency under the conditions of capacitor mismatch and comparator input noise. With this algorithm, the signal-to-noise ratio has been increased by 7.3 dB, which is equivalent to 1.2 bit ENOB. The spurious-free dynamic range has been increased by 16.8 dB. Using the mathematical model when designing and debugging calibration algorithms speeds up these processes.