High-k Gate Stack Engineering and Low Frequency Noise Performance

Abstract

Gate stack engineering for deep submicron CMOS has been extensively studied, so that high-k dielectrics in combination with metal gate or FUSI electrodes are implemented in research lines. Much effort concentrated on the optimization of gate stacks from a viewpoint of dielectric properties and reliability. Less information is available on the low frequency noise performance of these gate stacks. This review demonstrates the necessity of gate stack engineering for achieving a low 1/f noise performance. The impact of processing parameters, such as thickness of the interfacial layer and the high-k oxide, bulk properties of the high-k layer, post deposition anneals, choice of gate electrode material will be addressed. Such a systematic study forms the basis for noise modeling as for these gate-dielectrics the standard noise models are no longer applicable. The impact on the noise of strain engineering to boost up the carrier mobility is also briefly discussed.