High isolation and high linearity double‐pole double‐throw CMOS switch matrix for Ka‐band wireless transceiver front‐end IC

Abstract

AbstractThis letter proposes a double‐pole double‐throw (DPDT) switch with high isolation and high linearity using a 65‐nm CMOS process. To improve the isolation, resonant inductors are employed for the core switches, which are composed of a single‐stacked NMOS with gate‐body floating techniques. And, the switch is controlled by a cross‐biasing technique to increment the power linearity. The active circuits are designed separately from the passive elements to reduce the interference. The core area of the proposed switch excluding all of the pads is 380 × 300 μm2. The minimum insertion loss is 2.57 dB at 23 GHz and maximum isolation is 39.7 dB at 26 GHz, respectively. The third‐order intermodulation intercept point (IIP3) is 37 dBm at 28 GHz.