High-frequency pattern extraction in digital integrated circuits using scanning electrostatic force microscopy

Abstract

The ability to perform noninvasive logic analysis at the internal points of integrated circuits is crucial in the design and test of advanced microelectronics. We present a noncontact scanning probe technique for extracting high-frequency digital patterns at internal points of an integrated circuit. The digital waveforms are determined by sensing the localized electrostatic force between a small probe and point on the circuit being measured. The force is monitored by detecting the deflection of the probe using a fiber-optic interferometer. The bandwidth of force measurements made using proximal probes are typically limited by the mechanical frequency response of the probe. In the presented instrument high-frequency bit-by-bit digital pattern measurements are enabled by using a pulse sampled heterodyne technique. In conjunction with a nulling approach, the technique is capable of measurements without complex calibration or probe positioning, and can be performed over passivated structures. A simple procedure is also presented which corrects errors due to nonidealities of the pulse sampling waveform. Using a probe with a kHz resonant frequency, Mbit/s patterns have been measured. Errors due to coupling from adjacent signal lines and due to surface charge effects are examined.