High‐efficient Reed–Solomon decoder design using recursive Berlekamp–Massey architecture

Abstract

This study presents a high-efficient Reed–Solomon (RS) decoder based on the recursive enhanced parallel inversionless Berlekamp–Massey algorithm architecture. Compared with the conventional enhanced parallel inversionless Berlekamp–Massey algorithm architecture, the proposed architecture consists of a single processing element and has very low hardware complexity. It also employs a new initialisation to reduce the latency. This architecture uses pipelined Galois–Field multipliers to improve the clock frequency. In addition, the proposed architecture also has the dynamic power saving feature. The proposed RS (255, 239) decoder has been developed and implemented with SMIC 0.18-μm CMOS technology. The synthesis results show that the decoder requires about 13K gates and can operate at 575 MHz to achieve the data rate of 4.6 Gb/s. The proposed RS (255, 239) decoder is at least 28.15% more efficient than the previously related designs.