High-Efficiency Harmonically Terminated Diode and Transistor Rectifiers

Abstract

This paper presents a theoretical analysis of harmonically terminated high-efficiency power rectifiers and experimental validation on a class-C single Schottky-diode rectifier and a class- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\hbox{F}}^{-1}$</tex></formula> GaN transistor rectifier. The theory is based on a Fourier analysis of current and voltage waveforms, which arise across the rectifying element when different harmonic terminations are presented at its terminals. An analogy to harmonically terminated power amplifier (PA) theory is discussed. From the analysis, one can obtain an optimal value for the dc load given the RF circuit design. An upper limit on rectifier efficiency is derived for each case as a function of the device on-resistance. Measured results from fundamental frequency source–pull measurement of a Schottky diode rectifier with short-circuit terminations at the second and third harmonics are presented. A maximal device rectification efficiency of 72.8% at 2.45 GHz matches the theoretical prediction. A 2.14-GHz GaN HEMT rectifier is designed based on a class- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{F}}^{-1}$</tex></formula> PA. The gate of the transistor is terminated in an optimal impedance for self-synchronous rectification. Measurements of conversion efficiency and output dc voltage for varying gate RF impedance, dc load, and gate bias are shown with varying input RF power at the drain. The rectifier demonstrates an efficiency of 85% for a 10-W input RF power at the transistor drain with a dc voltage of 30 V across a 98- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\Omega$</tex></formula> resistor.