High Density Interconnection for Heterogeneous Integration on FOWLP Platform

Abstract

This paper describe a new packaging approach of achieving high density interconnect between ASIC and memory module through the use of embedded fine pitch interconnect chip (EFI) in redistribution layer first (RDL-first) fan-out wafer level (FOWLP) packaging platform. The EFI chip provides multiple layer of high density interconnect from 2 $\mu {\mathrm{ m}}$ to 0.4 $\mu {\mathrm{ m}}$ Cu line, to meet data rate of 2Gbps between ASIC and High Bandwidth Memory (HBM) module of 55 $\mu {\mathrm{ m}}$ bump pitch. The paper will provide package description, high density design consideration for the EFI and its integration with RDL layers, supported by electrical and structural mechanical simulations for optimizing data rate and wafer processing integration.