High-Density Electron-Beam-Fabricated CCD Memory Components

Abstract

We have designed, fabricated, and tested CCD circuit components and arrays suitable for use in making high-density (>256-kbit) memory chips. A novel multiplex/demultiplex circuit allows smaller parallel-column widths than those in SPS arrays made using the same design rules, yet exacts no penalty in terms of extra mask levels or clocking requirements. A detector/refresher circuit which uses a novel charge comparison principle with feedback provides 5-mV sensitivity at 1-MHz. CCD array structures have been fabricated with transfer-pair electrode sizes of 4.8 /spl mu/m and channel widths of 5.4 /spl mu/m that exhibit a charge-transfer efficiency of 0.9996 with no fat zero. This cell size would enable one to build a 256-kbit memory on a chip less than 40 000 mil/sup 2/. A combined electron-beam and photolithographic process has been developed to make high-resolution double-level polysilicon CCD's. A "universal" chip was used to interface the electron-beam and optical patterns. The combined lithography process reduces the throughput requirements for the electron-beam machines. It is also flexible so that lithography steps can be eliminated if only electron-beam or only optically defined devices are desired. We found that when process overetch, lithography size, and alignment do not improve proportionally, topological constraints arise preventing simple two-dimensional scaling. The design of a serial-parallel-serial (SPS) CCD is an example of this constraint.