High-Breakdown, High- $f_{\mathrm{ max}}$ Multiport Stacked-Transistor Topologies for the ${W}$ -Band Power Amplifiers

Abstract

Effect of silicon technology limitations, including transistor nonidealities, layout parasitics, and low-quality factor on-chip passive components on millimeter wave stacked switching power amplifiers operating at the W-band frequencies (75-110 GHz), is presented in this paper. To mitigate the performance degradation in output power and PAE arising from such causes, high-breakdown voltage, high-f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> multiport stacked-transistor topologies are proposed for realizing power amplifiers with high output power and high efficiency at 75-110 GHz. A 90-nm silicon germanium (SiGe) BiCMOS process is used to propose active structures comprising of two and three stacked transistors with integrated layout parasitics that achieve f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> and breakdown voltage of 295 GHz and 8 V and 260 GHz and 11 V, respectively. Functionality of such multiport transistor topologies is demonstrated in proof-of-concept implementations, including a five-stage two-stacked switching power amplifier (PA) that achieves peak output power and PAE of 22 dBm and 19% at 85 GHz, and a six-stage three-stacked PA that achieves peak output power and PAE of 23.3 dBm and 17% at 83 GHz, respectively. For comparison with conventional switching PA designs using native transistor footprints, a five-stage W-band nonstacked Class-E amplifiers is also fabricated in the same 90-nm SiGe BiCMOS process with output power and PAE of 19.5 dBm and 16% at 88 GHz. The superior performance of output power and PAE in designs using the multiport transistor topologies highlights the benefit of the proposed approach.