Hierarchical motion estimation algorithms with especially low hardware costs

Abstract

The digital signal processor (DSP) or video signal processor (VSP) is becoming a popular solution for video encoding because of its flexibility compared with the special purpose chip. The less hardware costs an algorithm requires, the better the algorithm is. The computational complexity, on-chip memory size requirement, the amount of data fetch and the data fetch times are used as the measurement of the encoding algorithms performance. Considering that, a large-scale-subsample (4:1 horizontally and vertically subsampling) hierarchical motion estimation algorithm (LSS-HME) is proposed. It can be implemented with less hardware resources. In order to improve the estimation performance the relativity of the motion vector field is exploited. The peak signal-to-noise ratio (PSNR) degradation of the reconstructed image is limited to about 0.1 dB compared with the full search (FS) algorithm. By using the simple motion estimation algorithm described, MPEG-2 MP@ML or even higher layers can be implemented on the mainstream video signal processor with quite good performance.