Heterostructure Source-Gated Transistors: Challenges in Design and Fabrication

Abstract

Source-gated transistors (SGTs) [1, 2] use a potential barrier at the source to produce low-voltage saturation and flat saturated characteristics. This, in turn, results in excellent power efficiency and amplification performance [3-5]. Usually, SGTs are made with a Schottky source contact which acts as the current-control mechanism. These devices are easy to fabricate in a multitude of semiconductor systems, but may suffer, depending on design, from reduced dynamic range of the current above the threshold, and from significant temperature dependence of the on-current. We propose an alternative method of making SGTs, using an ohmic source contact and a bulk barrier. We call devices realised following this principle bulk unipolar barrier source-gated transistors (BUSGTs). Several strategies for realising the bulk barrier exist, which depend on the material system and fabrication process considered [6]. Here, we realise the bulk barrier at the source with a tri-layer semiconductor heterostructure (Figure 1, top). The advantages of this architecture include improved dynamic range (Figure 1, bottom) and reduced temperature dependence of drain current, as well as the usual energy and gain characteristics of SGTs. Measurement results on C70/C60/C70 n-type devices show: low hysteresis, indicating good quality interfaces; a large threshold shift due to the bulk barrier and residual charge in the heterostructure; and FET-like saturation, due to the interplay between semiconductor mobility and barrier height. A strong correlation is found between measurements and simulations using Silvaco Atlas. We discuss the benefits of such structures, and also the fabrication and design challenges associated with this type of transistor (chemistry and materials, barrier realisation, interface properties, requirements on charge carrier mobility). [1] S. D. Brotherton, Introduction to Thin Film Transistors: Physics and Technology of TFTs, Springer, 453–480, Cham (2013); [2] A. Valletta et al., J. Appl. Phys. 114 064501 (2013); [3] R. A. Sporea et al., Scientific Reports 4 4295 (2014); [4] R. A. Sporea, ULSI vs TFT V (2015); [5] R. A. Sporea et al., AA3.07, MRS Fall, Boston (2015); [6] J. M. Shannon, APL 35 (1) 63–65 (1979). Figure 1 – Top: fabricated tri-layer fullerene heterostructure, showing the position of the bulk barrier at the source; bottom: transfer characteristic of the fabricated devices, illustrating high dynamic range above threshold, low hysteresis, and significant threshold shift as due to the bulk barrier. Figure 1