Abstract

Quilt Packaging (QP) is a direct chip-to-chip edge-interconnect technology that offers extremely low interconnect loss and can be implemented on a variety of substrates. We report here the experimental demonstration of heterogeneous integration between Si and GaAs substrates. Ultrawide-bandwidth Quilt Packaging coplanar waveguide interconnects between Si and GaAs chips are presented along with preliminary thermal shock data. Fabricated structures on ∼100 µm thick Si and GaAs chips exhibited chip-to-chip insertion losses below 0.5 dB up to 170 GHz, and below 1 dB up to 220 GHz from on-chip S-parameter measurements. Simulated results on a heterogeneous Si-GaAs quilted chipset on scaled QP interconnect exhibited chip-to-chip insertion losses below 0.5 dB up to 300 GHz, and below 1.5 dB up to 750 GHz. Despite the coefficient of thermal expansion mismatch between Si and GaAs, the interconnects also exhibited no adverse effects from thermal shock testing through 1250 cycles.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call