Heterogeneous Integration of Photonic Integrated Circuits Using 3D Assembly Techniques: Silicon Technology and Packaging

Abstract

The large internet companies' investments indicate an ongoing increase of data-based business volume through the next decades with the rise of the internet of things and the continuous growth of communication and data facilities. The two-figure yearly growth rate of exchanged data volume within data centers is challenging the actual short distance communication paradigms. With datacenter architectures getting larger and “flatter”, the availability of high bandwidth, low power and low cost optical links ranging from less than 1 meter to 1 kilometer is a key issue. It is therefore expected that today's 10 Gb/s transceiver data rate soon increase to 28Gb/s, 40 Gb/s and beyond. For such a channel bandwidth, the copper-based wires are no longer suitable in terms of cost, power and bandwidth density. Optical interconnects are expected to replace copper for short distances below 500 m and down to 1 m within servers and between servers of the same data center. They exhibit much higher scalability and flexibility in terms of bandwidth, reach and lower energy consumption down to 1 pJ/b and below. The integration of optical transceivers close to the computational logic is therefore becoming more and more attractive. The enabling technology for optical interconnect is silicon photonics which is maturing and leveraging the well-established knowledge coming from silicon technology. We today have a complete set of silicon photonics technology modules that cover passive components including multiplexers/demultiplexers, coupling functions, photodetectors, modulators and integrated laser sources. Given the constraints coming from the supply chain, we consider a heterogeneous integration of the photonics (PIC) and the electrical integrated circuits (EIC) within a single package, differentiating from a co-integration of both of them on a single die demonstrated in the past, which is not a viable nor scalable option from the economical point of view. Thereby we leverage our expertise in the 3D integration field, and we use a full set of mature technology modules including through-silicon vias (TSV), wafer thinning and micro-bumping. These modules have only been used in the past within electrical circuits, but their implantation in photonics chips has no showstoppers. The 3D integration enables a stacking of the electrical drivers in the EIC die on top of the photodiodes and modulators in the PIC die. The small micro-bump size reduces the parasitic capacitances and enables an optimized electro-optical co-design. The TSV enable the connection of the stack with the rest of the package and to the second-level interconnect with low inductive losses, thus boosting the system performance. The advanced 3D packaging technique also enables the alignment and attachment of the optical fibers using silicon micro-ferrules. Today's active alignment techniques for optical coupling are time-consuming and expensive, and not compatible with usual micro-electronics techniques. The ongoing development of silicon micro-ferrules with mechanical micro-bumps enables a compatible assembly of the optical plugs with the remaining system and a quick assembly process with standard pick-and-place equipment. The paper will introduce today's system demand in the data base market and its translation into technology requirements. It will then survey our silicon photonics technology modules and actual demonstrations. We will then introduce the packaging constraints and the impact of 3D integration on the system assembly. Finally, we will present our advances in terms of packaging of optical micro-connectors.