Heated ion implantation for high-performance and highly reliable silicon-on-insulator complementary metal–oxide–silicon fin field-effect transistors

Abstract

We have investigated the impact of heated ion implantation (I/I) on the performance and reliability of silicon-on-insulator (SOI) complementary metal–oxide–silicon (CMOS) fin field-effect transistors (FinFETs). An implantation temperature equal to and higher than 400 °C is needed to maintain the crystallinity of the Si substrate during I/I within the experimental conditions of ion species, implantation energy, and ion dose in this study. By heated I/I at 500 °C, the 11-nm-thick SOI layer perfectly maintains the crystallinity even after I/I, and a defect-free crystal is obtained by activation annealing. It was clarified that the cap layer is essential for the suppression of the out-diffusion during heated I/I. Heated I/I on the source and drain improves the on-current–off-current (Ion–Ioff), threshold voltage (Vth) variability, and bias temperature instability (BTI) characteristics of nMOS and pMOS FinFETs as compared with those after room-temperature I/I.