Abstract

Chemically amplified resists are used for 248 nm, 193 nm, immersion and extreme ultraviolet (UV) lithography. Among many process steps, post exposure bake (PEB) is the key process to make the desired small line width and critical dimension control. During PEB, the de-protection reaction and acid diffusion are determined by bake temperature and time. One of the key factors that determines the de-protection and acid diffusion is the initial temperature rising of the hot plate. The unpredictable temperature rising to the pre-set temperature is the main cause of line width variation. In order to predict the accurate PEB temperature and time dependency to the line width, the heat transfer from the hot plate to the resist on top of the silicon wafer is studied. Numerical approach is used to solve the heat conduction problem. Only the boundary temperature values are needed to solve this conduction, the information inside each layer is not required. We calculated the temperature rising characteristics of the photoresist on top of the several layers of the mask. The air conductivity, air gap, number of layers underneath the resist, thickness of the wafer, thickness of the layer including the resist, and different kind of layers are varied to see the characteristics of the bake temperature rising. We showed that there was small temperature difference at photoresist among the layer stack and thickness variation, even though it was very small. There is a strong possibility that this small PEB temperature difference would cause serious critical dimension (CD) control problem.

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