Hücre Başına Çoklu Bit Media Geliştirmek İçin Nano Ölçekli Yarı İletken Bir Aygıtın Sonlu Eleman Modellemesi

Abstract

Generally, a semiconductor device using chalcogenide elements as a fundamental components is considered as a potentially revelation technology for future ultra-high density data storage technology. These kind of device having high contrast between 0 and 1 logic states brought out the possible application of the idea of multiple logic levels in a single bit in an effort to boost data storage density. The potential stabilization of resistance levels in between the logic states enables storage of several data in a single cell (such as 00, 01, 10, 11 levels). I report on investigation of the role of the current injection and material selection in stabilizing middle resistance states within a nanoscale semiconductor cell for fabrication of a multiple-bit-per-cell through 3D finite element modeling. First, to visualize the complex nature of the switching dynamics, 3D finite element simulations were carried out in cell with two active layers Ge2Sb2Te5/Ge2Sb2Te5 (GST/GST) alloys incorporating phase change kinetics, electrical, thermal and percolation. Simulation was constructed by using an iterative approach with coupled differential equations, which are all as a function of temperature, as well as Seebeck coefficient to account for thermoelectric effect. The complex nature of switching dynamics appears highly sensitive to the exact programming voltage and material properties. The model suggests that the physical origin of the formation of stable middle states unexpectedly in circular top contact devices is mainly due to anisotropic heating during the application of a programming current pulse. The model successfully predicts the required programing conditions and the importantce of material selection for such mixed-phase levels, which can be used to optimize memory cells for future ultra-high-density data storage applications.