Harmonic-Invariant Scaling Method for Power Electronic Converters in Power Hardware-in-the-Loop Test Beds

Abstract

Power hardware-in-the-loop (PHIL) is an experimental technique that uses power amplifiers and real-time simulators for studying the dynamics of power electronic converters and electrical grids. PHIL tests provide the means for functional validation of advanced control algorithms without the burden of building high-power prototypes during early TRL. However, replicating the behavior of high-power systems with laboratory SDC can be complex. Inaccurate scaling of the SDC coupled with an exclusive focus on instantaneous voltages and currents at the fundamental frequency can lead to PHIL results that are only partially relatable to the high-power systems under study. Test beds that fail to represent switching frequency harmonics cannot be used for studying harmonic penetration or loss characterization of large-scale converters. To tackle this issue, this paper proposes a harmonic-invariant scaling method (HISM) that exploits the VA rating of preexisting laboratory SDCs for more accurately replicating harmonic phenomena in a PHIL test bench. Firstly,, a theoretical analysis of the proposed method is presented and, subsequently, the method is validated with MATLAB simulations and experimental tests.