Hardware study and implementation of image encryption algorithm based on a hyperchaotic key generator

Abstract

In today’s interconnected world, digital data transmissions are an integral part of our communication systems. Connected objects are commonly used in digital life, however, they can be vulnerable to hacking and personal data theft due to inadequate security. To address the size and capability limitations of existing embedded devices, lightweight cryptography has been developed. This paper presents a hardware implementation of a lightweight cryptographic method using VHDL and FPGAs to secure digital information, specifically images. The proposed algorithm is a block cipher scheme that operates on blocks of 128-bit length and employs chaos based generator-based. The cryptosystem includes a whitening operation, random permutation, and key-dependent Substitution box. The proposed hardware implementation of the algorithm was validated using a Xilinx FPGA-Zynq platform and can secure different gray-scale images while maintaining low power usage, a high frequency of 160.6098 MHz, and high throughput of 11314.917 Mbps. The cryptosystem is shown to be effective against statistical and differential attacks, and key sequences are tested using the NIST SP 800–22 test suite. The algorithm’s robustness with respect to Shannon’s theory and Chaos is discussed, emphasizing its high level of security and performance.