Abstract
The automatic implementation of fast operating PLCs with massive parallel hardware processing is expected by wide range of designers not familiar with details of computation algorithms design in hardware. The paper presents an approach to implement the fixed point arithmetic computations of control programs with ability of computation resource sharing. The method is based on developed intermediate graph representation for PLC programming languages. The graph representation of a PLC program allows to reveal and to implement parallel computations. Presented methods are dedicated for FPGA architectures and enables utilization of pipelined processing. It is based on multiple stages scheduling shown in detail. Presented methods are intended to improve the efficiency of computation resource utilization of the direct mapping method. The paper is concluded with experiments results that compare achieved performance and resource requirements.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
