Abstract

The recent expansion of the Internet of Things is creating a new world of smart devices in which security implications are very significant. Besides the claimed security level, the IoT devices are usually featured with constrained resources, such as low computation capability, low memory, and limited battery. Lightweight cryptographic primitives are proposed in the context of IoT while considering the trade-off between security guarantee and good performance. In this paper, we present optimized hardware, lightweight cryptographic designs, of 32-bit datapath, LED 64/128, SIMON 64/128, and SIMECK 64/128 algorithms, for constrained devices. Our proposed designs are investigated on Spartan-3, Spartan-6, and Zynq-7000 FPGA platforms in terms of area, speed, efficiency, and power consumption. The proposed designs achieved a high throughput up to 891.99 Mbps, 838.95 Mbps, and 210.13 Mbps for SIMECK 64/128, SIMON 64/128, and LED 64/128 on Zynq-7000, respectively. A deep comparison between our three proposed designs is elaborated on different FPGA families for adequate FPGAs-based application deployment. Test results and security analysis show that not only can our proposed designs achieve good encryption results with high performance and a low reduced cost but also they are secure enough to resist statistical attacks.

Highlights

  • Traditional secure encryption methods are usually calculated intensively with large key sizes which undermine the computation capacity of IoT devices

  • E main focus of this work is to propose an optimized hardware implementation of lightweight cryptographic designs and examine the effect on hardware architectures, the area, power, efficiency, and performance of hardware implementations on low-cost Xilinx FPGA platforms. ree different hardware architectures of Light Encryption Device (LED) 64/128, SIMON 64/ 128, and SIMECK 64/128 algorithms have been proposed in this study. e security level is evaluated by implementing

  • To the best of our knowledge and based on literature review, this work sets the best performances of hardware lightweight cryptographic cipher architectures. e architectures we have proposed are implemented with 32-bit datapath on different platforms for an adequate device choice where FPGAs are deployed

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Summary

Related Works

There was a quick advancement of research and development of lightweight cryptography for implementation on devices with limited resources in IoT environments. e principal objective is to design and employ ultralightweight cryptographic algorithms that can be used in such applications while proving desired security levels. Cipher implementations targeted for low-resource applications are classified into software and hardware implementation. Kim et al [13] investigated lightweight features of HIGHT block cipher and presented the optimized implementations of both software and hardware for low-end IoT platforms, including resource-constrained devices (8-bit AVR and 32-bit ARM Cortex-M3) and application-specific integrated circuit (ASIC). Another research presented by Abed et al [15] proposes implementing, optimizing, and modeling SIMON cipher design for low-resource devices, with an emphasis on energy and power, which are critical metrics for low-resource devices. Almost all cited works are interested in optimizing the software or hardware implementation for low area occupation, high-speed calculation, high throughput, or other metrics, but in any work, all performances are respected at the same time neither with a reasonable security level guaranty

Proposed Lightweight Cryptographic Architecture
32 Key d dn–1
Experimental Results
Security Analysis
Conclusion and Future
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