Abstract
This paper presents a hardware implementation of Elliptic Curve Cryptography (ECC) with optimized scalar multiplication. In elliptic curve cryptography, scalar multiplication is an important and most time-consuming operation that dominates the ECC performance. In this paper, the scalar multiplication is carried out using the Vedic multiplier for finite field multiplication operation to improvise the performance. The proposed architecture is implemented and evaluated for the performance evaluation parameters—area, delay, and power consumption. To evaluate the efficiency of the proposed design, the results are compared with Karatsuba based ECC design. The comparative results show that ECC using Vedic multiplier outperform then Karatsuba based ECC for the area, delay and power consumption. The elliptic curve cryptosystem is implemented over GF(2m) binary field for B-233 field size, which is more secured according to NIST Digital Signature Standards. The cryptosystem is designed in Verilog HDL, synthesized and simulated using Xilinx 13.2 IDE on Virtex6 FPGA device.
Published Version
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